Re: [PATCH v6 1/2] dt-bindings: net: Add FSD EQoS device tree bindings

[Krzysztof Kozlowski <krzk@xxxxxxxxxx>]

On Thu, Feb 13, 2025 at 10:16:23AM +0530, Swathi K S wrote:
> +  clock-names:
> +    minItems: 5
> +    maxItems: 10
> +    contains:
> +      enum:
> +        - ptp_ref
> +        - master_bus
> +        - slave_bus
> +        - tx
> +        - rx
> +        - master2_bus
> +        - slave2_bus
> +        - eqos_rxclk_mux
> +        - eqos_phyrxclk
> +        - dout_peric_rgmii_clk

This does not match the previous entry. It should be strictly ordered
with minItems: 5.


> +
> +  iommus:
> +    maxItems: 1
> +
> +  phy-mode:
> +    enum:
> +      - rgmii-id
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - iommus
> +  - phy-mode
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/fsd-clk.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        ethernet1: ethernet@14300000 {
> +            compatible = "tesla,fsd-ethqos";
> +            reg = <0x0 0x14300000 0x0 0x10000>;
> +            interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> +            interrupt-names = "macirq";
> +            clocks = <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>,
> +                     <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>,
> +                     <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>,
> +                     <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>,
> +                     <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>,
> +                     <&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>,
> +                     <&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>,
> +                     <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>,
> +                     <&clock_peric PERIC_EQOS_PHYRXCLK>,
> +                     <&clock_peric PERIC_DOUT_RGMII_CLK>;
> +            clock-names = "ptp_ref", "master_bus", "slave_bus","tx",
> +                          "rx", "master2_bus", "slave2_bus", "eqos_rxclk_mux",
> +                          "eqos_phyrxclk","dout_peric_rgmii_clk";
> +            pinctrl-names = "default";
> +            pinctrl-0 = <&eth1_tx_clk>, <&eth1_tx_data>, <&eth1_tx_ctrl>,
> +                        <&eth1_phy_intr>, <&eth1_rx_clk>, <&eth1_rx_data>,
> +                        <&eth1_rx_ctrl>, <&eth1_mdio>;
> +            iommus = <&smmu_peric 0x0 0x1>;
> +            phy-mode = "rgmii-id";
> +       };

Misaligned/misindented.

Best regards,
Krzysztof