Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8
counters and a very different event layout compared to the M1 PMU.
Interrupts are delivered as IRQs instead of FIQs like on the M1.
Signed-off-by: Nick Chan <towinchenmi@xxxxxxxxx>
---
drivers/perf/apple_m1_cpu_pmu.c | 178 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 178 insertions(+)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index 12eba1075b36768afc29e211926331b9a426c54f..f852cd5633d7f180dc9dbdde11332ec825a3d558 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -18,6 +18,7 @@
#include <asm/irq_regs.h>
#include <asm/perf_event.h>
+#define A7_PMU_NR_COUNTERS 8
#define M1_PMU_NR_COUNTERS 10
#define APPLE_PMU_MAX_NR_COUNTERS 10
@@ -44,6 +45,143 @@
* know next to nothing about the events themselves, and we already have
* per cpu-type PMU abstractions.
*/
+
+enum a7_pmu_events {
+ A7_PMU_PERFCTR_INST_ALL = 0x0,
+ A7_PMU_PERFCTR_UNKNOWN_1 = 0x1,
+ A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
+ A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0x10,
+ A7_PMU_PERFCTR_L2_TLB_MISS_DATA = 0x11,
+ A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE = 0x19,
+ A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE = 0x20,
+ A7_PMU_PERFCTR_L2C_AGENT_LD = 0x22,
+ A7_PMU_PERFCTR_L2C_AGENT_LD_MISS = 0x23,
+ A7_PMU_PERFCTR_L2C_AGENT_ST = 0x24,
+ A7_PMU_PERFCTR_L2C_AGENT_ST_MISS = 0x25,
+ A7_PMU_PERFCTR_SCHEDULE_UOP = 0x58,
+ A7_PMU_PERFCTR_MAP_REWIND = 0x61,
+ A7_PMU_PERFCTR_MAP_STALL = 0x62,
+ A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x6e,
+ A7_PMU_PERFCTR_INST_A32 = 0x78,
+ A7_PMU_PERFCTR_INST_T32 = 0x79,
+ A7_PMU_PERFCTR_INST_A64 = 0x7a,
+ A7_PMU_PERFCTR_INST_BRANCH = 0x7b,
+ A7_PMU_PERFCTR_INST_BRANCH_CALL = 0x7c,
+ A7_PMU_PERFCTR_INST_BRANCH_RET = 0x7d,
+ A7_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x7e,
+ A7_PMU_PERFCTR_INST_BRANCH_INDIR = 0x81,
+ A7_PMU_PERFCTR_INST_BRANCH_COND = 0x82,
+ A7_PMU_PERFCTR_INST_INT_LD = 0x83,
+ A7_PMU_PERFCTR_INST_INT_ST = 0x84,
+ A7_PMU_PERFCTR_INST_INT_ALU = 0x85,
+ A7_PMU_PERFCTR_INST_SIMD_LD = 0x86,
+ A7_PMU_PERFCTR_INST_SIMD_ST = 0x87,
+ A7_PMU_PERFCTR_INST_SIMD_ALU = 0x88,
+ A7_PMU_PERFCTR_INST_LDST = 0x89,
+ A7_PMU_PERFCTR_UNKNOWN_8d = 0x8d,
+ A7_PMU_PERFCTR_UNKNOWN_8e = 0x8e,
+ A7_PMU_PERFCTR_UNKNOWN_8f = 0x8f,
+ A7_PMU_PERFCTR_UNKNOWN_90 = 0x90,
+ A7_PMU_PERFCTR_UNKNOWN_93 = 0x93,
+ A7_PMU_PERFCTR_UNKNOWN_94 = 0x94,
+ A7_PMU_PERFCTR_UNKNOWN_95 = 0x95,
+ A7_PMU_PERFCTR_L1D_TLB_ACCESS = 0x96,
+ A7_PMU_PERFCTR_L1D_TLB_MISS = 0x97,
+ A7_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0x98,
+ A7_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0x99,
+ A7_PMU_PERFCTR_UNKNOWN_9b = 0x9b,
+ A7_PMU_PERFCTR_LD_UNIT_UOP = 0x9c,
+ A7_PMU_PERFCTR_ST_UNIT_UOP = 0x9d,
+ A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0x9e,
+ A7_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
+ A7_PMU_PERFCTR_LDST_X64_UOP = 0xa7,
+ A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xb4,
+ A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xb5,
+ A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xb6,
+ A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xb9,
+ A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xba,
+ A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xbb,
+ A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xbd,
+ A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xbf,
+ A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xc0,
+ A7_PMU_PERFCTR_UNKNOWN_c1 = 0xc1,
+ A7_PMU_PERFCTR_UNKNOWN_c4 = 0xc4,
+ A7_PMU_PERFCTR_UNKNOWN_c5 = 0xc5,
+ A7_PMU_PERFCTR_UNKNOWN_c6 = 0xc6,
+ A7_PMU_PERFCTR_UNKNOWN_c8 = 0xc8,
+ A7_PMU_PERFCTR_UNKNOWN_ca = 0xca,
+ A7_PMU_PERFCTR_UNKNOWN_cb = 0xcb,
+ A7_PMU_PERFCTR_FED_IC_MISS_DEMAND = 0xce,
+ A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xcf,
+ A7_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
+ A7_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
+ A7_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
+ A7_PMU_PERFCTR_UNKNOWN_f8 = 0xf8,
+ A7_PMU_PERFCTR_UNKNOWN_fd = 0xfd,
+ A7_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
+ /*
+ * From this point onwards, these are not actual HW events,
+ * but attributes that get stored in hw->config_base.
+ */
+ A7_PMU_CFG_COUNT_USER = BIT(8),
+ A7_PMU_CFG_COUNT_KERNEL = BIT(9),
+};
+
+static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] = {
+ [0 ... A7_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
+ [A7_PMU_PERFCTR_INST_ALL] = ANY_BUT_0_1 | BIT(1),
+ [A7_PMU_PERFCTR_UNKNOWN_1] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0),
+ [A7_PMU_PERFCTR_INST_A32] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_T32] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_A64] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_INT_ST] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_INT_ALU] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_SIMD_ALU] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_INST_LDST] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_8d] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_8e] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_8f] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_90] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_93] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_94] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_95] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_9b] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_LD_UNIT_UOP] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_9f] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c1] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c4] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c5] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c6] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_c8] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_ca] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_cb] = ONLY_5_6_7,
+ [A7_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6,
+ [A7_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6,
+ [A7_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6,
+ [A7_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
+};
+
enum m1_pmu_events {
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
@@ -162,6 +300,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] = {
[M1_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
};
+static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] = {
+ PERF_MAP_ALL_UNSUPPORTED,
+ [PERF_COUNT_HW_CPU_CYCLES] = A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE,
+ [PERF_COUNT_HW_INSTRUCTIONS] = A7_PMU_PERFCTR_INST_ALL,
+ [PERF_COUNT_HW_BRANCH_MISSES] = A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = A7_PMU_PERFCTR_INST_BRANCH
+};
+
static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] = {
PERF_MAP_ALL_UNSUPPORTED,
[PERF_COUNT_HW_CPU_CYCLES] = M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE,
@@ -491,6 +637,12 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc,
return -EAGAIN;
}
+static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc,
+ struct perf_event *event)
+{
+ return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity);
+}
+
static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
struct perf_event *event)
{
@@ -514,6 +666,11 @@ static void __m1_pmu_set_mode(u8 mode)
isb();
}
+static void a7_pmu_start(struct arm_pmu *cpu_pmu)
+{
+ __m1_pmu_set_mode(PMCR0_IMODE_AIC);
+}
+
static void m1_pmu_start(struct arm_pmu *cpu_pmu)
{
__m1_pmu_set_mode(PMCR0_IMODE_FIQ);
@@ -548,6 +705,11 @@ static int apple_pmu_map_event_63(struct perf_event *event,
return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT);
}
+static int a7_pmu_map_event(struct perf_event *event)
+{
+ return apple_pmu_map_event_47(event, &a7_pmu_perf_map);
+}
+
static int m1_pmu_map_event(struct perf_event *event)
{
return apple_pmu_map_event_47(event, &m1_pmu_perf_map);
@@ -573,6 +735,11 @@ static void apple_pmu_reset_common(void *info, u32 counters)
isb();
}
+static void a7_pmu_reset(void *info)
+{
+ apple_pmu_reset_common(info, A7_PMU_NR_COUNTERS);
+}
+
static void m1_pmu_reset(void *info)
{
apple_pmu_reset_common(info, M1_PMU_NR_COUNTERS);
@@ -615,6 +782,16 @@ static int apple_pmu_init_common(struct arm_pmu *cpu_pmu, u32 counters)
}
/* Device driver gunk */
+static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu)
+{
+ cpu_pmu->name = "apple_cyclone_pmu";
+ cpu_pmu->get_event_idx = a7_pmu_get_event_idx;
+ cpu_pmu->map_event = a7_pmu_map_event;
+ cpu_pmu->reset = a7_pmu_reset;
+ cpu_pmu->start = a7_pmu_start;
+ return apple_pmu_init_common(cpu_pmu, A7_PMU_NR_COUNTERS);
+}
+
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
{
cpu_pmu->name = "apple_icestorm_pmu";
@@ -660,6 +837,7 @@ static const struct of_device_id m1_pmu_of_device_ids[] = {
{ .compatible = "apple,blizzard-pmu", .data = m2_pmu_blizzard_init, },
{ .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, },
{ .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, },
+ { .compatible = "apple,cyclone-pmu", .data = a7_pmu_cyclone_init, },
{ },
};
MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids);
--
2.48.1
