On 11/02/2025 16:17, Matthew Gerlach wrote: > Add a device tree enabling PCIe Root Port support on an Agilex F-series > Development Kit which has the P-tile variant of the PCIe IP. > > Signed-off-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx> > --- > v6: > - Fix SPDX header. ... > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts > new file mode 100644 > index 000000000000..3588c845cf9c > --- /dev/null > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts > @@ -0,0 +1,87 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2024, Intel Corporation > + */ > + > +#include "socfpga_agilex.dtsi" > +#include "socfpga_agilex_socdk.dtsi" > +#include "socfpga_agilex_pcie_root_port.dtsi" > + Missing compatible, missing model, missing bindings. Best regards, Krzysztof
