On Mon, Feb 10, 2025 at 11:09:41PM +0100, Alexander Sverdlin wrote:
> Make the peripheral device tree re-usable on ARM64 platform by moving CPU
> core and interrupt controllers' parts into the respective per-SoC .dtsi
> files.
>
> Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nubering
> into "plic" interrupt-controller numbering.
>
> Have a nice refactoring side-effect that "plic" and "clint" "compatible"
> property is not specified outside of the corresponding device itself.
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@xxxxxxxxx>
> ---
> Changelog:
> v2:
> - instead of carving out peripherals' part, carve out ARCH-specifics (CPU
> core, interrupt controllers) and spread them among 3 SoC .dtsi files which
> included cv18xx.dtsi;
> - define a label for the "soc" node and use it in the newly introduced DTs;
>
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 64 ++++++++++++---
> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 64 ++++++++++++---
> arch/riscv/boot/dts/sophgo/cv181x.dtsi | 2 +-
> arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 91 ++++++----------------
> arch/riscv/boot/dts/sophgo/sg2002.dtsi | 64 ++++++++++++---
> 6 files changed, 240 insertions(+), 102 deletions(-)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index aa1f5df100f0..eef2884b36f9 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -3,6 +3,8 @@
> * Copyright (C) 2023 Jisheng Zhang <jszhang@xxxxxxxxxx>
> */
>
> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> +
> #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
> #include "cv18xx.dtsi"
>
> @@ -14,22 +16,62 @@ memory@80000000 {
> reg = <0x80000000 0x4000000>;
> };
>
> - soc {
> - pinctrl: pinctrl@3001000 {
> - compatible = "sophgo,cv1800b-pinctrl";
> - reg = <0x03001000 0x1000>,
> - <0x05027000 0x1000>;
> - reg-names = "sys", "rtc";
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <25000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <65536>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> };
> };
> };
Make all soc definition include the common cpu file.
Not just copy it.
>
> -&plic {
> - compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> -};
> +&soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
>
> -&clint {
> - compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> + pinctrl: pinctrl@3001000 {
> + compatible = "sophgo,cv1800b-pinctrl";
> + reg = <0x03001000 0x1000>,
> + <0x05027000 0x1000>;
> + reg-names = "sys", "rtc";
> + };
> +
> + plic: interrupt-controller@70000000 {
> + compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@74000000 {
> + compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> };
>
> &clk {
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> index 8a1b95c5116b..54f7e229bcd8 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> @@ -3,6 +3,8 @@
> * Copyright (C) 2023 Inochi Amaoto <inochiama@xxxxxxxxxxx>
> */
>
> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> +
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
> #include "cv18xx.dtsi"
> @@ -16,22 +18,62 @@ memory@80000000 {
> reg = <0x80000000 0x10000000>;
> };
>
> - soc {
> - pinctrl: pinctrl@3001000 {
> - compatible = "sophgo,cv1812h-pinctrl";
> - reg = <0x03001000 0x1000>,
> - <0x05027000 0x1000>;
> - reg-names = "sys", "rtc";
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <25000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <65536>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> };
> };
> };
>
> -&plic {
> - compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> -};
> +&soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
>
> -&clint {
> - compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> + pinctrl: pinctrl@3001000 {
> + compatible = "sophgo,cv1812h-pinctrl";
> + reg = <0x03001000 0x1000>,
> + <0x05027000 0x1000>;
> + reg-names = "sys", "rtc";
> + };
> +
> + plic: interrupt-controller@70000000 {
> + compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@74000000 {
> + compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> };
>
> &clk {
> diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> index 5fd14dd1b14f..bbdb30653e9a 100644
> --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
> @@ -11,7 +11,7 @@ soc {
> emmc: mmc@4300000 {
> compatible = "sophgo,cv1800b-dwcmshc";
> reg = <0x4300000 0x1000>;
> - interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_AXI4_EMMC>,
> <&clk CLK_EMMC>;
> clock-names = "core", "bus";
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> new file mode 100644
> index 000000000000..a68d61131efb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@xxxxxxxxxx>
> + * Copyright (C) 2023 Inochi Amaoto <inochiama@xxxxxxxxxxx>
> + */
> +
> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> +
> +/ {
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <25000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <65536>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +};
> +
> +&soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
> +
> + plic: interrupt-controller@70000000 {
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@74000000 {
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> +};
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index c18822ec849f..62c1464a0490 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -12,47 +12,16 @@ / {
> #address-cells = <1>;
> #size-cells = <1>;
>
> - cpus: cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - timebase-frequency = <25000000>;
> -
> - cpu0: cpu@0 {
> - compatible = "thead,c906", "riscv";
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-block-size = <64>;
> - d-cache-sets = <512>;
> - d-cache-size = <65536>;
> - i-cache-block-size = <64>;
> - i-cache-sets = <128>;
> - i-cache-size = <32768>;
> - mmu-type = "riscv,sv39";
> - riscv,isa = "rv64imafdc";
> - riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> -
> - cpu0_intc: interrupt-controller {
> - compatible = "riscv,cpu-intc";
> - interrupt-controller;
> - #interrupt-cells = <1>;
> - };
> - };
> - };
> -
> osc: oscillator {
> compatible = "fixed-clock";
> clock-output-names = "osc_25m";
> #clock-cells = <0>;
> };
>
> - soc {
> + soc: soc {
> compatible = "simple-bus";
> - interrupt-parent = <&plic>;
> #address-cells = <1>;
> #size-cells = <1>;
> - dma-noncoherent;
> ranges;
>
> clk: clock-controller@3002000 {
> @@ -75,7 +44,7 @@ porta: gpio-controller@0 {
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> - interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
> };
> };
>
> @@ -93,7 +62,7 @@ portb: gpio-controller@0 {
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
> };
> };
>
> @@ -111,7 +80,7 @@ portc: gpio-controller@0 {
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
> };
> };
>
> @@ -129,7 +98,7 @@ portd: gpio-controller@0 {
> reg = <0>;
> interrupt-controller;
> #interrupt-cells = <2>;
> - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
> };
> };
>
> @@ -137,7 +106,7 @@ saradc: adc@30f0000 {
> compatible = "sophgo,cv1800b-saradc";
> reg = <0x030f0000 0x1000>;
> clocks = <&clk CLK_SARADC>;
> - interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> status = "disabled";
> @@ -162,7 +131,7 @@ i2c0: i2c@4000000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
> clock-names = "ref", "pclk";
> - interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -173,7 +142,7 @@ i2c1: i2c@4010000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
> clock-names = "ref", "pclk";
> - interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -184,7 +153,7 @@ i2c2: i2c@4020000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
> clock-names = "ref", "pclk";
> - interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -195,7 +164,7 @@ i2c3: i2c@4030000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
> clock-names = "ref", "pclk";
> - interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -206,14 +175,14 @@ i2c4: i2c@4040000 {
> #size-cells = <0>;
> clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
> clock-names = "ref", "pclk";
> - interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> uart0: serial@4140000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04140000 0x100>;
> - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -224,7 +193,7 @@ uart0: serial@4140000 {
> uart1: serial@4150000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04150000 0x100>;
> - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -235,7 +204,7 @@ uart1: serial@4150000 {
> uart2: serial@4160000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04160000 0x100>;
> - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -246,7 +215,7 @@ uart2: serial@4160000 {
> uart3: serial@4170000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04170000 0x100>;
> - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -261,7 +230,7 @@ spi0: spi@4180000 {
> #size-cells = <0>;
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
> clock-names = "ssi_clk", "pclk";
> - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -272,7 +241,7 @@ spi1: spi@4190000 {
> #size-cells = <0>;
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
> clock-names = "ssi_clk", "pclk";
> - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -283,7 +252,7 @@ spi2: spi@41a0000 {
> #size-cells = <0>;
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
> clock-names = "ssi_clk", "pclk";
> - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> @@ -294,14 +263,14 @@ spi3: spi@41b0000 {
> #size-cells = <0>;
> clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
> clock-names = "ssi_clk", "pclk";
> - interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
>
> uart4: serial@41c0000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x041c0000 0x100>;
> - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
> clock-names = "baudclk", "apb_pclk";
> reg-shift = <2>;
> @@ -312,7 +281,7 @@ uart4: serial@41c0000 {
> sdhci0: mmc@4310000 {
> compatible = "sophgo,cv1800b-dwcmshc";
> reg = <0x4310000 0x1000>;
> - interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_AXI4_SD0>,
> <&clk CLK_SD0>;
> clock-names = "core", "bus";
> @@ -322,7 +291,7 @@ sdhci0: mmc@4310000 {
> sdhci1: mmc@4320000 {
> compatible = "sophgo,cv1800b-dwcmshc";
> reg = <0x4320000 0x1000>;
> - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_AXI4_SD1>,
> <&clk CLK_SD1>;
> clock-names = "core", "bus";
> @@ -332,7 +301,7 @@ sdhci1: mmc@4320000 {
> dmac: dma-controller@4330000 {
> compatible = "snps,axi-dma-1.01a";
> reg = <0x04330000 0x1000>;
> - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
> clock-names = "core-clk", "cfgr-clk";
> #dma-cells = <1>;
> @@ -344,19 +313,5 @@ dmac: dma-controller@4330000 {
> snps,data-width = <4>;
> status = "disabled";
> };
> -
> - plic: interrupt-controller@70000000 {
> - reg = <0x70000000 0x4000000>;
> - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <2>;
> - riscv,ndev = <101>;
> - };
> -
> - clint: timer@74000000 {
> - reg = <0x74000000 0x10000>;
> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> - };
> };
> };
> diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> index 7f79de33163c..732d0e72cf13 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
> @@ -3,6 +3,8 @@
> * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@xxxxxxxxxxx>
> */
>
> +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
> +
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
> #include "cv18xx.dtsi"
> @@ -16,22 +18,62 @@ memory@80000000 {
> reg = <0x80000000 0x10000000>;
> };
>
> - soc {
> - pinctrl: pinctrl@3001000 {
> - compatible = "sophgo,sg2002-pinctrl";
> - reg = <0x03001000 0x1000>,
> - <0x05027000 0x1000>;
> - reg-names = "sys", "rtc";
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <25000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <65536>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> };
> };
> };
>
> -&plic {
> - compatible = "sophgo,sg2002-plic", "thead,c900-plic";
> -};
> +&soc {
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
>
> -&clint {
> - compatible = "sophgo,sg2002-clint", "thead,c900-clint";
> + pinctrl: pinctrl@3001000 {
> + compatible = "sophgo,sg2002-pinctrl";
> + reg = <0x03001000 0x1000>,
> + <0x05027000 0x1000>;
> + reg-names = "sys", "rtc";
> + };
> +
> + plic: interrupt-controller@70000000 {
> + compatible = "sophgo,sg2002-plic", "thead,c900-plic";
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@74000000 {
> + compatible = "sophgo,sg2002-clint", "thead,c900-clint";
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> };
>
> &clk {
> --
> 2.48.1
>
