The One-Time Programmable (OTP) Memory Controller (OTPC) is the secure
interface between the system and the OTP memory. It also features the
Unique Product ID (UID) registers containing a unique serial number.
See datasheet (DS60001579G) sections "7. Memories" and "23. OTP Memory
Controller (OTPC)" for reference.
Signed-off-by: Alexander Dahl <ada@xxxxxxxxxxx>
---
Notes:
v2:
- squashed with patch adding the clock properties
arch/arm/boot/dts/microchip/sam9x60.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi
index 1724b79967a17..af859f0b83a0f 100644
--- a/arch/arm/boot/dts/microchip/sam9x60.dtsi
+++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/clock/microchip,sam9x60-pmc.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
/ {
#address-cells = <1>;
@@ -157,6 +158,15 @@ sdmmc1: sdio-host@90000000 {
status = "disabled";
};
+ otpc: efuse@eff00000 {
+ compatible = "microchip,sam9x60-otpc", "syscon";
+ reg = <0xeff00000 0xec>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&pmc PMC_TYPE_CORE SAM9X60_PMC_MAIN_RC>, <&pmc PMC_TYPE_PERIPHERAL 46>;
+ clock-names = "main_rc_osc", "otpc_clk";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
--
2.39.5
