The PPE (packet process engine) hardware block is available in Qualcomm IPQ chipsets that support PPE architecture, such as IPQ9574 and IPQ5332. The PPE in the IPQ9574 SoC includes six ethernet ports (6 GMAC and 6 XGMAC), which are used to connect with external PHY devices by PCS. The PPE also includes packet processing offload capabilities for various networking functions such as route and bridge flows, VLANs, different tunnel protocols and VPN. It also includes an L2 switch function for bridging packets among the 6 ethernet ports and the CPU port. The CPU port enables packet transfer between the ethernet ports and the ARM cores in the SoC, using the ethernet DMA. This patch series is the first part of a three part series that will together enable Ethernet function for IPQ9574 SoC. While support is initially being added for IPQ9574 SoC, the driver will be easily extendable to enable Ethernet support for other IPQ SoC such as IPQ5332. The driver can also be extended later for adding support for L2/L3 network offload features that the PPE can support. The functionality to be enabled by each of the three series (to be posted sequentially) is as below: Part 1: The PPE patch series (this series), which enables the platform driver, probe and initialization/configuration of different PPE hardware blocks. Part 2: The PPE MAC patch series, which enables the phylink operations for the PPE ethernet ports. Part 3: The PPE EDMA patch series, which enables the Rx/Tx Ethernet DMA and netdevice driver for the 6 PPE ethernet ports. A more detailed description of the functions enabled by part 1 is below: 1. Initialize PPE device hardware functions such as buffer management, queue management, scheduler and clocks in order to bring up PPE device. 2. Enable platform driver and probe functions 3. Register debugfs file to provide access to various PPE packet counters. These statistics are recorded by the various hardware process counters, such as port RX/TX, CPU code and hardware queue counters. 4. A detailed introduction of PPE along with the PPE hardware diagram in the first two patches (dt-bindings and documentation). Below is a reference to an earlier RFC discussion with the community about enabling ethernet driver support for Qualcomm IPQ9574 SoC. This writeup can help provide a higher level architectural view of various other drivers that support the PPE such as clock and PCS drivers. Topic: RFC: Advice on adding support for Qualcomm IPQ9574 SoC Ethernet. https://lore.kernel.org/linux-arm-msm/d2929bd2-bc9e-4733-a89f-2a187e8bf917@xxxxxxxxxxx/ Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx> --- Changes in v3: - Add the top-level ref ethernet-switch.yaml and remove node definition ethernet-ports in the DT binding file. - Remove unnecessary error message for devm_kzalloc(). - Reverse the mapping of BM ceiling bits. - Fix multicast queue start/end configurations. - Declare the SoC-specific PPE configuration variables as const. - Fix kernel documentation errors. - Fix the compile errors reported by gcc-14. - Improve the commit message of L2 bridge initialization and debugfs patches. - Link to v2: https://lore.kernel.org/r/20250108-qcom_ipq_ppe-v2-0-7394dbda7199@xxxxxxxxxxx Changes in v2: - Represent the PPE hardware hierarchy in dtbindings, add PPE hardware diagram. - Remove all SoC specific hardware properties from dtbindings since driver maintains them. - Move out the PCS (UNIPHY) handling into a separate PCS driver posted separately at below. https://lore.kernel.org/all/20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@xxxxxxxxxxx - Move out the PPE MAC patches into a separate series to limit patch count to 15 or less. (PPE MAC patches will be posted sequentially after this series). - Rename the hardware initialization related files from ppe_ops.c[h] to ppe_config.c[h] - Improve PPE driver documentation and diagram. - Fix dtbinding check errors. - Link to v1: https://lore.kernel.org/r/20240110114033.32575-1-quic_luoj@xxxxxxxxxxx --- Lei Wei (2): docs: networking: Add PPE driver documentation for Qualcomm IPQ9574 SoC net: ethernet: qualcomm: Initialize PPE L2 bridge settings Luo Jie (12): dt-bindings: net: Add PPE for Qualcomm IPQ9574 SoC net: ethernet: qualcomm: Add PPE driver for IPQ9574 SoC net: ethernet: qualcomm: Initialize PPE buffer management for IPQ9574 net: ethernet: qualcomm: Initialize PPE queue management for IPQ9574 net: ethernet: qualcomm: Initialize the PPE scheduler settings net: ethernet: qualcomm: Initialize PPE queue settings net: ethernet: qualcomm: Initialize PPE service code settings net: ethernet: qualcomm: Initialize PPE port control settings net: ethernet: qualcomm: Initialize PPE RSS hash settings net: ethernet: qualcomm: Initialize PPE queue to Ethernet DMA ring mapping net: ethernet: qualcomm: Add PPE debugfs support for PPE counters MAINTAINERS: Add maintainer for Qualcomm PPE driver .../devicetree/bindings/net/qcom,ipq9574-ppe.yaml | 406 ++++ .../networking/device_drivers/ethernet/index.rst | 1 + .../device_drivers/ethernet/qualcomm/ppe/ppe.rst | 197 ++ MAINTAINERS | 8 + drivers/net/ethernet/qualcomm/Kconfig | 15 + drivers/net/ethernet/qualcomm/Makefile | 1 + drivers/net/ethernet/qualcomm/ppe/Makefile | 7 + drivers/net/ethernet/qualcomm/ppe/ppe.c | 234 +++ drivers/net/ethernet/qualcomm/ppe/ppe.h | 39 + drivers/net/ethernet/qualcomm/ppe/ppe_config.c | 2002 ++++++++++++++++++++ drivers/net/ethernet/qualcomm/ppe/ppe_config.h | 317 ++++ drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c | 692 +++++++ drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.h | 16 + drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 559 ++++++ 14 files changed, 4494 insertions(+) --- base-commit: acdefab0dcbc3833b5a734ab80d792bb778517a0 change-id: 20250108-qcom_ipq_ppe-aa4c4fa0ab73 Best regards, -- Luo Jie <quic_luoj@xxxxxxxxxxx>
