The VOP on RK3328 needs to run at a higher rate in order to produce
a proper 3840x2160 signal.
Change to use 300MHz for VIO clk and 400MHz for VOP clk.
Fixes: 0f2ddb128fa2 ("arm64: dts: rockchip: Increase VOP clk rate on RK3328")
Signed-off-by: Elaine Zhang <zhangqing@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 7d992c3c01ce..0c905f411e92 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -842,7 +842,8 @@
<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru HCLK_PERI>, <&cru PCLK_PERI>,
- <&cru SCLK_RTC32K>;
+ <&cru SCLK_RTC32K>, <&cru ACLK_VIO_PRE>,
+ <&cru ACLK_VOP_PRE>;
assigned-clock-parents =
<&cru HDMIPHY>, <&cru PLL_APLL>,
<&cru PLL_GPLL>, <&xin24m>,
@@ -852,8 +853,8 @@
<0>, <24000000>,
<24000000>, <24000000>,
<15000000>, <15000000>,
- <300000000>, <100000000>,
- <400000000>, <100000000>,
+ <100000000>, <100000000>,
+ <100000000>, <100000000>,
<50000000>, <100000000>,
<100000000>, <100000000>,
<50000000>, <50000000>,
@@ -863,7 +864,8 @@
<150000000>, <75000000>,
<75000000>, <150000000>,
<75000000>, <75000000>,
- <32768>;
+ <32768>, <300000000>,
+ <400000000>;
};
usb2phy_grf: syscon@ff450000 {
--
2.17.1
