On 7.02.2025 11:31 AM, Neil Armstrong wrote:
> The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper
> interrupt partition maps and use the 4th interrupt cell to pass the
> partition phandle for each ARM PMU node.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> ---
> @@ -5309,6 +5309,20 @@ intc: interrupt-controller@17100000 {
> #size-cells = <2>;
> ranges;
>
> + ppi-partitions {
> + ppi_cluster0: interrupt-partition-0 {
> + affinity = <&cpu0 &cpu1>;
> + };
> +
> + ppi_cluster1: interrupt-partition-1 {
> + affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>;
> + };
> +
> + ppi_cluster2: interrupt-partition-2 {
> + affinity = <&cpu7>;
> + };
I'm not sure this is accurate.
I *think* it's cores 0-1 and 2-7, but I can't find a concrete answer
Konrad
