Hi Bjorn,
On 17:44 Mon 03 Feb , Bjorn Helgaas wrote:
> On Mon, Jan 13, 2025 at 03:58:04PM +0100, Andrea della Porta wrote:
> > RaspberryPi RP1 is an MFD providing, among other peripherals, several
> > clock generators and PLLs that drives the sub-peripherals.
> > Add the driver to support the clock providers.
>
> > +#define PLL_PRIM_DIV1_SHIFT 16
> > +#define PLL_PRIM_DIV1_WIDTH 3
> > +#define PLL_PRIM_DIV1_MASK GENMASK(PLL_PRIM_DIV1_SHIFT + \
> > + PLL_PRIM_DIV1_WIDTH - 1, \
> > + PLL_PRIM_DIV1_SHIFT)
> > +
> > +#define PLL_PRIM_DIV2_SHIFT 12
> > +#define PLL_PRIM_DIV2_WIDTH 3
> > +#define PLL_PRIM_DIV2_MASK GENMASK(PLL_PRIM_DIV2_SHIFT + \
> > + PLL_PRIM_DIV2_WIDTH - 1, \
> > + PLL_PRIM_DIV2_SHIFT)
>
> Maybe this is standard drivers/clk style, but this seems like overkill
> to me. I think this would be sufficient and easier to read:
>
> #define PLL_PRIM_DIV1_MASK GENMASK(18, 16)
> #define PLL_PRIM_DIV2_MASK GENMASK(14, 12)
Ack.
>
> > +static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw,
> > + unsigned long parent_rate)
> > +{
> > + struct rp1_clk_desc *pll = container_of(hw, struct rp1_clk_desc, hw);
> > + struct rp1_clockman *clockman = pll->clockman;
> > + const struct rp1_pll_data *data = pll->data;
> > + u32 prim, prim_div1, prim_div2;
> > +
> > + prim = clockman_read(clockman, data->ctrl_reg);
> > + prim_div1 = (prim & PLL_PRIM_DIV1_MASK) >> PLL_PRIM_DIV1_SHIFT;
> > + prim_div2 = (prim & PLL_PRIM_DIV2_MASK) >> PLL_PRIM_DIV2_SHIFT;
>
> And then here, I think you can just use FIELD_GET():
>
> prim_div1 = FIELD_GET(PLL_PRIM_DIV1_MASK, prim);
> prim_div2 = FIELD_GET(PLL_PRIM_DIV2_MASK, prim);
>
> It looks like the same could be done for PLL_SEC_DIV_MASK,
> PLL_CS_REFDIV_SHIFT, PLL_PH_PHASE_SHIFT, CLK_CTRL_AUXSRC_MASK, etc.
Ack.
Regards,
Andrea
