From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Yo, This series is partly leveraging Clement's work adding a validate callback in the extension detection code so that things like checking for whether a vector crypto extension is usable can be done like: has_extension(<vector crypto>) rather than has_vector() && has_extension(<vector crypto>) which Eric pointed out was a poor design some months ago. The rest of this is adding some requirements to the bindings that prevent combinations of extensions disallowed by the ISA. There's a bunch of over-long lines in here, but I thought that the over-long lines were clearer than breaking them up. Cheers, Conor. v3: - rebase on v6.14-rc1 - split vector crypto validation patch into vector validation and vector crypto validation - fix zve64x requiring extension list to match Eric's PR v2: - Fix an inverted clause Clément pointed out - Add Zvbb validation, that I had missed accidentally - Drop the todo about checking the number of validation rounds, I tried in w/ qemu's max cpu and things looked right CC: Eric Biggers <ebiggers@xxxxxxxxxx> CC: Conor Dooley <conor@xxxxxxxxxx> CC: Rob Herring <robh@xxxxxxxxxx> CC: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx> CC: Paul Walmsley <paul.walmsley@xxxxxxxxxx> CC: Palmer Dabbelt <palmer@xxxxxxxxxxx> CC: "Clément Léger" <cleger@xxxxxxxxxxxx> CC: Andy Chiu <andybnac@xxxxxxxxx> CC: linux-riscv@xxxxxxxxxxxxxxxxxxx CC: devicetree@xxxxxxxxxxxxxxx CC: linux-kernel@xxxxxxxxxxxxxxx Conor Dooley (6): RISC-V: add vector extension validation checks RISC-V: add vector crypto extension validation checks RISC-V: add f & d extension validation checks dt-bindings: riscv: d requires f dt-bindings: riscv: add vector sub-extension dependencies dt-bindings: riscv: document vector crypto requirements .../devicetree/bindings/riscv/extensions.yaml | 85 +++++++++++ arch/riscv/include/asm/cpufeature.h | 3 + arch/riscv/kernel/cpufeature.c | 133 +++++++++++++----- 3 files changed, 183 insertions(+), 38 deletions(-) -- 2.45.2
