E Shattow wrote:
> Replace syscrg assignments of clocks, clock parents, and rates with
> default settings for compatibility with downstream boot loader SPL
> secondary program loader.
>
> Signed-off-by: E Shattow <e@xxxxxxxxxxxx>
> ---
> arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index 48fb5091b817..a5661b677687 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -359,9 +359,14 @@ spi_dev0: spi@0 {
> };
>
> &syscrg {
> - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
> - <&pllclk JH7110_PLLCLK_PLL0_OUT>;
> - assigned-clock-rates = <500000000>, <1500000000>;
> + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> + <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> + <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> + <&syscrg JH7110_SYSCLK_QSPI_REF>;
> + assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> + <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> + <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> + <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
I think Conor asked about this too, but you still don't write why it's ok to
drop the 500MHz and 1,5GHz assignments to the cpu-core and pll0 clocks
respectively. You should add this to the commit message itself.
/Emil
