Hi Geert Uytterhoeven,
> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 05 February 2025 08:17
> Subject: Re: [PATCH v2 4/8] arm64: dts: renesas: r9a09g047: Add SDHI0-SDHI2 nodes
>
> Hi Biju,
>
> On Fri, 31 Jan 2025 at 12:25, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > Add SDHI0-SDHI2 nodes to RZ/G3E ("R9A09G047") SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> > ---
> > v1->v2:
> > * Status of internal regulator is disabled in the SoC .dtsi. Override
> > the status in the board DTS when needed.
>
> Thanks for the update!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > @@ -410,6 +410,66 @@ gic: interrupt-controller@14900000 {
> > interrupt-controller;
> > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > };
> > +
> > + sdhi0: mmc@15c00000 {
> > + compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057";
> > + reg = <0x0 0x15c00000 0 0x10000>;
> > + interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
> > + <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
> > + clock-names = "core", "clkh", "cd", "aclk";
> > + resets = <&cpg 0xa7>;
> > + power-domains = <&cpg>;
> > + status = "disabled";
> > +
> > + vqmmc_sdhi0: vqmmc-regulator {
>
> sdhi0_vqmmc? (same for the others)
It is ok to me.
Cheers,
Biju
