Hi Tomi
>> Thanks for pointing out, I probably missed this since the use-case still
>> worked since VP interrupts were still enabled and those were sufficient to
>> drive the display
>> but the VID underflow interrupts and VID specific bits were probably not
>> enabled at-all due to above miss, so agreed
>> we should probably go ahead with a different reg space for AM62L due to
>> aforementioned differences.
>
> I think I disagree here. Afaiu, AM62L has plane at hw index 1 (VIDL1), but the
> plane at hw index 0 (VID1) is not instantiated in the hardware. But the
> registers are the same, i.e. AM62L's registers for VIDL1 match AM65x/AM62x
> registers, right?
>
> If so, we just need to tell the driver the hw index, instead of creating new
> register offsets as done in v2.
>
> Or am I missing something here? (I haven't looked at the HW manual yet).
>
No that's not the only difference. For AM62L, the VID_IRQENABLE/STATUS
registers start at +0x4 as compared to AM65x/AM62x/ :
AM62L:
[DISPC_VID_IRQENABLE_OFF] = 0x48,
[DISPC_VID_IRQSTATUS_OFF] = 0x5c,
AM62x/AM65x:
[DISPC_VID_IRQENABLE_OFF] = 0x44,
[DISPC_VID_IRQSTATUS_OFF] = 0x58,
So it seems okay to me to have a separate reg offset struct.
Regards
Devarsh
