The clock controller of SG2044 provides multiple clocks for various IPs on the SoC, including PLL, mux, div and gates. As the PLL and div have obvious changed and do not fit the framework of SG2042, a new implement is provided to handle these. Changed from v1: patch 1: 1. Applied Krzysztof's tag patch 2: 1. Fix the build warning from bot. Inochi Amaoto (2): dt-bindings: clock: sophgo: add clock controller for SG2044 clk: sophgo: Add clock controller support for SG2044 SoC .../bindings/clock/sophgo,sg2044-clk.yaml | 40 + drivers/clk/sophgo/Kconfig | 11 + drivers/clk/sophgo/Makefile | 1 + drivers/clk/sophgo/clk-sg2044.c | 2271 +++++++++++++++++ drivers/clk/sophgo/clk-sg2044.h | 62 + include/dt-bindings/clock/sophgo,sg2044-clk.h | 170 ++ 6 files changed, 2555 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml create mode 100644 drivers/clk/sophgo/clk-sg2044.c create mode 100644 drivers/clk/sophgo/clk-sg2044.h create mode 100644 include/dt-bindings/clock/sophgo,sg2044-clk.h -- 2.48.1
