On Tue, Jan 28, 2025 at 10:11 AM Conor Dooley <conor@xxxxxxxxxx> wrote:
>
> On Mon, Jan 27, 2025 at 08:59:50PM -0800, Atish Patra wrote:
> > Smcntrpmf extension allows M-mode to enable privilege mode filtering
> > for cycle/instret counters. However, the cyclecfg/instretcfg CSRs are
> > only available only in Ssccfg only Smcntrpmf is present.
> >
> > That's why, kernel needs to detect presence of Smcntrpmf extension and
> > enable privilege mode filtering for cycle/instret counters.
> >
> > Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
> > ---
> > arch/riscv/include/asm/hwcap.h | 1 +
> > arch/riscv/kernel/cpufeature.c | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 2f5ef1dee7ac..42b34e2f80e8 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -104,6 +104,7 @@
> > #define RISCV_ISA_EXT_SMCSRIND 95
> > #define RISCV_ISA_EXT_SSCCFG 96
> > #define RISCV_ISA_EXT_SMCDELEG 97
> > +#define RISCV_ISA_EXT_SMCNTRPMF 98
> >
> > #define RISCV_ISA_EXT_XLINUXENVCFG 127
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index b584aa2d5bc3..ec068c9130e5 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -394,6 +394,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
> > __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts),
> > __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
> > + __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF),
> > __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND),
>
> Isn't the order here wrong?
> * 3. Standard supervisor-level extensions (starting with 'S') must be listed
> * after standard unprivileged extensions. If multiple supervisor-level
> * extensions are listed, they must be ordered alphabetically.
Yeah. Fixed it. Thanks for catching.
