On Wed, Jan 22, 2025 at 12:04:10PM +0530, Varadarajan Narayanan wrote: > From: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx> > > Add phy and controller nodes for pcie0_x1 and pcie1_x2. > > Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx> > Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx> > Signed-off-by: Varadarajan Narayanan <quic_varada@xxxxxxxxxxx> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> One minor comment below. [...] > + assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>, > + <&gcc GCC_PCIE3X2_AXI_M_CLK>, > + <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>, > + <&gcc GCC_PCIE3X2_AXI_S_CLK>, > + <&gcc GCC_PCIE3X2_RCHG_CLK>; > + > + assigned-clock-rates = <2000000>, > + <266666666>, > + <240000000>, > + <240000000>, > + <100000000>; > + Does the drivers really need to set clock rate for these many clocks? No, as per the reply to my similar question to IPQ5424: https://lore.kernel.org/linux-arm-msm/9206e44c-da4f-4bdb-850f-fac511f4ddc7@xxxxxxxxxxx/ - Mani -- மணிவண்ணன் சதாசிவம்
