On 03/02/2025 15:18, Manivannan Sadhasivam wrote:
> On Mon, Jan 27, 2025 at 11:35:50AM -0600, Matthew Gerlach wrote:
>> From: "D M, Sharath Kumar" <sharath.kumar.d.m@xxxxxxxxx>
>>
>> Add PCIe root port controller support for the Agilex family of chips.
>> The Agilex PCIe IP has three variants that are mostly sw compatible,
>> except for a couple register offsets. The P-Tile variant supports
>> Gen3/Gen4 1x16. The F-Tile variant supports Gen3/Gen4 4x4, 4x8, and 4x16.
>> The R-Tile variant improves on the F-Tile variant by adding Gen5 support.
>>
>> To simplify the implementation of pci_ops read/write functions,
>> ep_{read/write}_cfg() callbacks were added to struct altera_pci_ops
>> to easily distinguish between hardware variants.
>>
>> Signed-off-by: D M, Sharath Kumar <sharath.kumar.d.m@xxxxxxxxx>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
>
> Driver changes LGTM! You just need to fix the checkpatch warnings as reported
> by krzk. With that,
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
I expected warnings, because of missing bindings, but there actually are
bindings, just some unusual order of patches, so maybe nothing to fix.
Anywy just in case: never mix DTS into the middle of patchset because it
just raises the question about dependency and you cannot have one. These
are different subsystems - DTS *always* goes to SoC.
Best regards,
Krzysztof
