On 3.02.2025 2:23 PM, Neil Armstrong wrote: > On the SM8650, the dynamic clock and voltage scaling (DCVS) is done in an > hardware controlled loop using the LMH and EPSS blocks with constraints and > OPPs programmed in the board firmware. > > Since the Hardware does a better job at maintaining the CPUs temperature > in an acceptable range by taking in account more parameters like the die > characteristics or other factory fused values, it makes no sense to try > and reproduce a similar set of constraints with the Linux cpufreq thermal > core. > > In addition, the tsens IP is responsible for monitoring the temperature > across the SoC and the current settings will heavily trigger the tsens > UP/LOW interrupts if the CPU temperatures reaches the hardware thermal > constraints which are currently defined in the DT. And since the CPUs > are not hooked in the thermal trip points, the potential interrupts and > calculations are a waste of system resources. > > Drop the current passive trip points and only leave the critical trip > point that will trigger a software system reboot before an hardware > thermal shutdown in the allmost impossible case the hardware DCVS cannot > handle the temperature surge. > > Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> Konrad
