On Wed, Jan 22, 2025 at 04:34:51PM +0100, Stefan Schmidt wrote: > On Thu, 9 Jan 2025 at 15:58, Johan Hovold <johan@xxxxxxxxxx> wrote: > > On Thu, Dec 12, 2024 at 05:21:22PM +0530, Dikshita Agarwal wrote: > > > Introduce support for Qualcomm new video acceleration hardware i.e. > > > iris, used for video stream decoding. > > > > > Note: A harmless onetime error log "Lucid PLL latch failed. Output may > > > be unstable!" is seen during bootup. It doesn't impact any video > > > usecase and is currently under discussion. > > > > This could be an indication that some resources are not described > > correctly and could potentially require both binding and driver changes > > to address. > > > > This is also something which could cause trouble later (e.g. during > > suspend) even if you manage to get the clock running after boot. > > > > Generally, you should not be introducing any new warnings; they are > > there to let you know that something is wrong. > > > > Where is this issue being discussed? > > > > I think we at least need a public analysis and understanding of the > > problem before merging this. > > Taniya Das proposed a patchset to reconfigure PLL in the clk-alpha-pll > which allows the videocc-sm8550 driver to configure it correctly. > https://lore.kernel.org/linux-arm-msm/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@xxxxxxxxxxx/T/ > > I tested the Iris driver with this patchset and I am no longer seeing > the Lucid PLL latch failed warning. Thanks for the pointer. Please make sure to reference this series (and summarise the underlying issue) when resending this series. Judging from a quick look the approach taken there seems like a bit of a hack so it may not get merged in its current form. IIUC fixing the PLL issue properly may depend on adding support for multiple power domains to the clock drivers. Johan
