On 29/01/2025 17:37, Thierry Bultel wrote: > Document RZ/T2H (a.k.a r9a09g077) CPG (Clock Pulse Generator) binding. > Add the header file for the resets and clocks definitions. > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx> > --- > .../bindings/clock/renesas,rzt2h-cpg.yaml | 73 +++++++++ > include/dt-bindings/clock/r9a09g077-cpg.h | 144 ++++++++++++++++++ > 2 files changed, 217 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml > create mode 100644 include/dt-bindings/clock/r9a09g077-cpg.h > > diff --git a/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml > new file mode 100644 > index 000000000000..9a3a00126d2b > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml > @@ -0,0 +1,73 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/renesas,rzt2h-cpg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/T2H(P) Clock Pulse Generator (CPG) > + > +maintainers: > + - Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx> > + > +description: > + On Renesas RZ/T2H SoCs, the CPG (Clock Pulse Generator) handles generation > + and control of clock signals for the IP modules, generation and control of resets, Wrap at 80. See Coding style doc. > + and control over booting, low power consumption and power supply domains. > + > +properties: > + compatible: > + const: renesas,r9a09g077-cpg ... > +#define R9A09G077_SHOSTIF_MASTER_RST 13 > +#define R9A09G077_SHOSTIF_SLAVE_RST 14 > +#define R9A09G077_SHOSTIF_IP_RST 15 > +#define R9A09G077_DDRSS_RST_N_RST 16 > +#define R9A09G077_DDRSS_PWROKIN_RST 17 > +#define R9A09G077_DDRSS_RST_RST 18 > +#define R9A09G077_DDRSS_AXI0_RST 19 > +#define R9A09G077_DDRSS_AXI1_RST 20 > +#define R9A09G077_DDRSS_AXI2_RST 21 > +#define R9A09G077_DDRSS_AXI3_RST 22 > +#define R9A09G077_DDRSS_AXI4_RST 23 > +#define R9A09G077_DDRSS_MC_RST 24 > +#define R9A09G077_PCIE_RST 25 > +#define R9A09G077_DDRSS_PHY_RST 26 > + > +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ > \ No newline at end of file Patch warning here. Best regards, Krzysztof
