Document RZ/T2H (a.k.a r9a09g077) in SCI binding. Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx> --- .../bindings/serial/renesas,rzsci.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzsci.yaml diff --git a/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml new file mode 100644 index 000000000000..70e83bbcc79d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Serial Communication Interface + +maintainers: + - Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx> + - Geert Uytterhoeven <geert+renesas@xxxxxxxxx> + +allOf: + - $ref: serial.yaml# + +description: | + The SCI is configurable to asynchronous and synchronous serial + interfaces: + - Asynchronous interfaces (UART and Asynchronous Communications Interface + Adapter (ACIA)) + - 8-bit clock synchronous interface + - Simple I2C (master-only) + - Simple SPI + - Smart card interface + - Manchester mode + - Asynchronous interfaces (UART, RS485 and Asynchronous Communications + Interface Adapter (ACIA)) + The smart card interface complies with the ISO/IEC 7816-3 standard for + electronic signals and transmission protocol. Each SCI has FIFO buffers to + enable continuous and full-duplex communication, and the data transfer speed + can be configured independently using a baud rate generator. + +properties: + compatible: + const: renesas,r9a09g077-sci # RZ/T2H + + reg: + maxItems: 1 + + interrupts: + items: + - description: Error interrupt + - description: Receive buffer full interrupt + - description: Transmit buffer empty interrupt + - description: Transmit end interrupt + + interrupt-names: + items: + - const: eri + - const: rxi + - const: txi + - const: tei + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - fck # UART functional clock + - sck # optional external clock input + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a09g077-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + aliases { + serial0 = &sci0; + }; + + sci0: serial@80005000 { + compatible = "renesas,r9a09g077-sci"; + reg = <0x80005000 0x400>; + interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A09G077_SCI0_CLK>; + clock-names = "fck"; + power-domains = <&cpg>; + }; -- 2.43.0
