On 1/28/2025 5:09 PM, Konrad Dybcio wrote:
> On 25.01.2025 4:59 AM, Manikanta Mylavarapu wrote:
>> Enable the PCIe controller and PHY nodes corresponding to RDP466.
>>
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@xxxxxxxxxxx>
>> ---
>> Changes in V3:
>> - No change.
>>
>> arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 41 ++++++++++++++++++++-
>> 1 file changed, 40 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
>> index b6e4bb3328b3..73e6b38ecc26 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
>> @@ -53,6 +53,30 @@ &dwc_1 {
>> dr_mode = "host";
>> };
>>
>> +&pcie2 {
>> + pinctrl-0 = <&pcie2_default_state>;
>> + pinctrl-names = "default";
>> +
>> + perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>
> Please add a new line before 'status'
>
Okay, sure.
>> +};
>> +
>> +&pcie2_phy {
>> + status = "okay";
>> +};
>> +
>> +&pcie3 {
>> + pinctrl-0 = <&pcie3_default_state>;
>> + pinctrl-names = "default";
>> +
>> + perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +};
>> +
>> +&pcie3_phy {
>> + status = "okay";
>> +};
>> +
>> &qusb_phy_0 {
>> vdd-supply = <&vreg_misc_0p925>;
>> vdda-pll-supply = <&vreg_misc_1p8>;
>> @@ -147,6 +171,22 @@ data-pins {
>> bias-pull-up;
>> };
>> };
>> +
>> + pcie2_default_state: pcie2-default-state {
>> + pins = "gpio31";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + output-low;
>> + };
>> +
>> + pcie3_default_state: pcie3-default-state {
>> + pins = "gpio34";
>> + function = "gpio";
>> + drive-strength = <8>;
>> + bias-pull-up;
>> + output-low;
>
> The GPIO APIs are in control of in/out state instead, please remove the
> last property from both entries
Okay, sure.
Thanks & Regards,
Manikanta.
