Hi Biju,
Thanks for your patch!
On Tue, 28 Jan 2025 at 11:47, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
> SoC is almost identical to the one found on the RZ/V2H SoC, with the
> following differences:
> - The TINT register offset is 0x830 compared to 0x30 on RZ/V2H.
The first TINT register is at offset 0x820 vs. 0x20.
Perhaps:
- The TINT register base offset is 0x800 instead of zero.
> - The number of supported GPIO interrupts for TINT selection is 141
> instead of 86.
> - The pin index and TINT selection index are not in the 1:1 map
> - The number of TSSR registers is 15 instead of 8
> - Each TSSR register can program 2 TINTs instead of 4 TINTs
>
> Hence new compatible string "renesas,r9a09g047-icu" is added for RZ/G3E
> SoC.
>
> Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
The rest LGTM, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
