On 1/27/25 9:13 AM, Jonathan Santos wrote:
> When the device is configured to Sinc5 filter and decimation x8,
> output data is reduced to 16-bits in order to support 1 MHz of
> sampling frequency due to clock limitation.
>
> Use multiple scan types feature to enable the driver to switch
> scan type in runtime, making possible to support both 24-bit and
> 16-bit resolution.
>
> Signed-off-by: Jonathan Santos <Jonathan.Santos@xxxxxxxxxx>
> ---
> v2 Changes:
> * Included the ".shift" value back to scan_type.
> * Changed the number of bytes from regmap_read instead of shifting the
> ADC sample value when the word size is lower (16-bits).
> ---
> drivers/iio/adc/ad7768-1.c | 73 ++++++++++++++++++++++++++++++++------
> 1 file changed, 62 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c
> index e3ea078e6ec4..7686556c7808 100644
> --- a/drivers/iio/adc/ad7768-1.c
> +++ b/drivers/iio/adc/ad7768-1.c
> @@ -136,6 +136,15 @@ struct ad7768_clk_configuration {
> enum ad7768_pwrmode pwrmode;
> };
>
> +enum ad7768_scan_type {
> + AD7768_SCAN_TYPE_NORMAL,
> + AD7768_SCAN_TYPE_HIGH_SPEED,
> +};
> +
> +static const int ad7768_mclk_div_rates[4] = {
> + 16, 8, 4, 2,
> +};
> +
> static const struct ad7768_clk_configuration ad7768_clk_config[] = {
> { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE },
> { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE },
> @@ -150,6 +159,23 @@ static const struct ad7768_clk_configuration ad7768_clk_config[] = {
> { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE },
> };
>
> +static const struct iio_scan_type ad7768_scan_type[] = {
> + [AD7768_SCAN_TYPE_NORMAL] = {
> + .sign = 's',
> + .realbits = 24,
> + .storagebits = 32,
> + .shift = 8,
> + .endianness = IIO_BE,
> + },
> + [AD7768_SCAN_TYPE_HIGH_SPEED] = {
> + .sign = 's',
> + .realbits = 16,
> + .storagebits = 32,
Why not make storagebits 16 here?
> + .shift = 16,
> + .endianness = IIO_BE,
> + },
> +};
> +
