Hi Dmitry,
On 2025/1/23 19:32, Dmitry Baryshkov wrote:
On Thu, Jan 23, 2025 at 06:07:47PM +0800, Damon Ding wrote:
Add the necessary DT changes to enable eDP0 on RK3588S EVB1 board:
- Set pinctrl of pwm12 for backlight
- Enable edp0/hdptxphy0/vp2
- Assign the parent of DCLK_VOP2_SRC to PLL_V0PLL
- Add aux-bus/panel nodes
For RK3588, the PLL_V0PLL is specifically designed for the VOP2. This
means the clock rate of PLL_V0PLL can be adjusted according to the dclk
rate of relevant VP. It is typically assigned as the dclk source of a
specific VP when the clock of relevant display mode is unusual, such as
the eDP panel 'lg,lp079qx1-sp0v' paired with RK3588S EVB1, which has a
clock rate of 202.02MHz.
Signed-off-by: Damon Ding <damon.ding@xxxxxxxxxxxxxx>
---
Changes in v2:
- Remove brightness-levels and default-brightness-level properties in
backlight node.
- Add the detail DT changes to commit message.
Changes in v3:
- Use aux-bus instead of platform bus for edp-panel.
Changes in v4:
- Add comments related to the use of panel compatible "lg,lp079qx1-sp0v"
in the commit message.
Changes in v5:
- Use "edp-panel" instead of "lg,lp079qx1-sp0v"
- Remove unnecessary comments in commit message
- Assign the parent of DCLK_VOP2_SRC to PLL_V0PLL
Changes in v6:
- Add PLL_V0PLL related descriptions in commit message
---
.../boot/dts/rockchip/rk3588s-evb1-v10.dts | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
index bc4077575beb..a8c151b41e21 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
#include <dt-bindings/usb/pd.h>
#include "rk3588s.dtsi"
@@ -238,6 +239,41 @@ &combphy2_psu {
status = "okay";
};
+&edp0 {
+ force-hpd;
Why? Please mention the reason in the commit message.
The 'force-hpd' is set for edp0 because the HPD pin on the panel side is
not connected to the eDP HPD pin on the SoC side according to the
RK3588S EVB1 hardware design.
And I will add this description to the commit message in the next version.
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ backlight = <&backlight>;
+ power-supply = <&vcc3v3_lcd_edp>;
+
+ port {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&edp_out_panel>;
+ };
+ };
+ };
+ };
+};
+
+&edp0_in {
+ edp0_in_vp2: endpoint {
+ remote-endpoint = <&vp2_out_edp0>;
+ };
+};
+
+&edp0_out {
+ edp_out_panel: endpoint {
+ remote-endpoint = <&panel_in_edp>;
+ };
+};
+
+&hdptxphy0 {
+ status = "okay";
+};
+
&i2c3 {
status = "okay";
@@ -399,6 +435,7 @@ usbc0_int: usbc0-int {
};
&pwm12 {
+ pinctrl-0 = <&pwm12m1_pins>;
status = "okay";
};
@@ -1168,3 +1205,20 @@ usbdp_phy0_dp_altmode_mux: endpoint@1 {
};
};
};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP2_SRC>;
+ assigned-clock-parents = <&cru PLL_V0PLL>;
+ status = "okay";
+};
+
+&vp2 {
+ vp2_out_edp0: endpoint@ROCKCHIP_VOP2_EP_EDP0 {
+ reg = <ROCKCHIP_VOP2_EP_EDP0>;
+ remote-endpoint = <&edp0_in_vp2>;
+ };
+};
--
2.34.1
Best regards,
Damon
