This RFC adds support for l1-cache entry in device tree. The changes are
based on the assumptions that nodes will have l1-cache to describe first
cache layer. This patch enable to describe shared caches for SMTs which
is not currently possible about which there were discussions already
[1,2,3].
The question that I am seeking feedback for is to see if this might be a
good way to go about solving this issue? Or instead using phandle and
index in CPU nodes is a better way to go according to prior discussion,
I have another patch this investigates this approach [2]. Apparently,
every single CPU will need to addressed in the cpu-map structure as per
Mark mentioned earlier [4].
Sample device tree:
cpu@0 {
next-level-cache = <0x800b>;
phandle = <0x800a>;
reg = <0x00>;
enable-method = "psci";
compatible = "arm,cortex-a57";
device_type = "cpu";
l1-cache {
next-level-cache = <0x8008>;
cache-level = <0x01>;
d-cache-sets = <0x100>;
d-cache-block-size = <0x40>;
d-cache-size = <0x10000>;
i-cache-sets = <0x100>;
i-cache-block-size = <0x40>;
i-cache-size = <0x10000>;
phandle = <0x800b>;
};
};
cpu@1 {
next-level-cache = <0x8009>;
phandle = <0x8007>;
reg = <0x01>;
enable-method = "psci";
compatible = "arm,cortex-a57";
device_type = "cpu";
l1-cache {
next-level-cache = <0x8008>;
cache-level = <0x01>;
d-cache-sets = <0x100>;
d-cache-block-size = <0x40>;
d-cache-size = <0x10000>;
i-cache-sets = <0x100>;
i-cache-block-size = <0x40>;
i-cache-size = <0x10000>;
phandle = <0x8009>;
};
l2-cache {
next-level-cache = <0x8002>;
cache-level = <0x02>;
cache-unified;
cache-sets = <0x800>;
cache-block-size = <0x40>;
cache-size = <0x100000>;
phandle = <0x8008>;
};
};
1) https://lore.kernel.org/linux-devicetree/CAL_JsqLGEvGBQ0W_B6+5cME1UEhuKXadBB-6=GoN1tmavw9K_w@xxxxxxxxxxxxxx/
2) https://lore.kernel.org/linux-arm-kernel/20250110161057.445-1-alireza.sanaee@xxxxxxxxxx/
3) https://mail.gnu.org/archive/html/qemu-arm/2025-01/msg00014.html
4) https://lore.kernel.org/linux-arm-kernel/Z4FJZPRg75YIUR2l@J2N7QTR9R3/
Alireza Sanaee (1):
base/of/cacheinfo: support l1 entry in dt
drivers/base/cacheinfo.c | 54 +++++++++++++++++++++++++++-------------
1 file changed, 37 insertions(+), 17 deletions(-)
--
2.34.1
