Hi Elaine,
On 2025-01-24 07:46, Elaine Zhang wrote:
> The VOP on RK3328 needs to run at a higher rate in order to produce
> a proper 3840x2160 signal.
> Change to use 300MHz for VIO clk and 400MHz for VOP clk.
It is probably better to merge this change and the prior revert into a
single patch with a Fixes-tag for the commit 0f2ddb128fa2 ("arm64: dts:
rockchip: Increase VOP clk rate on RK3328") to ensure this change get
backported correctly.
Regards,
Jonas
>
> Fixes: 4b6764f200f2 ("Revert "arm64: dts: rockchip: Increase VOP clk
> rate on RK3328"")
>
> Signed-off-by: Elaine Zhang <zhangqing@xxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> index f3ef8cbfbdae..0c905f411e92 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
> @@ -842,7 +842,8 @@
> <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
> <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
> <&cru HCLK_PERI>, <&cru PCLK_PERI>,
> - <&cru SCLK_RTC32K>;
> + <&cru SCLK_RTC32K>, <&cru ACLK_VIO_PRE>,
> + <&cru ACLK_VOP_PRE>;
> assigned-clock-parents =
> <&cru HDMIPHY>, <&cru PLL_APLL>,
> <&cru PLL_GPLL>, <&xin24m>,
> @@ -863,7 +864,8 @@
> <150000000>, <75000000>,
> <75000000>, <150000000>,
> <75000000>, <75000000>,
> - <32768>;
> + <32768>, <300000000>,
> + <400000000>;
> };
>
> usb2phy_grf: syscon@ff450000 {
