Some controllers and endpoints provide provision to program the entry delays of L0s & L1 which will allow the link to enter L0s & L1 more aggressively to save power. Per PCIe r6.0, sec 4.2.5.1, during Link training, a PCIe component captures the N_FTS value it receives. Per 4.2.5.6, when transitioning the Link from L0s to L0, it must transmit N_FTS Fast Training Sequences to enable the receiver to obtain bit and Symbol lock. Components may have device-specific ways to configure N_FTS values to advertise during Link training. Define an n_fts array with an entry for each supported data rate. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx> --- changes in v2:- - Split N_FTS & L1 and L0s entry delay in two patches (bjorn) - Update the commit text, description (bjorn) Krishna Chaitanya Chundru (2): schemas: pci: bridge: Document PCI L0s & L1 entry delay schemas: pci: bridge: Document PCIe N_FTS dtschema/schemas/pci/pci-bus-common.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.34.1
