On Thu, Jan 23, 2025 at 02:58:01PM +0530, Charan Pedumuru wrote: > From: Durai Manickam KR <durai.manickamkr@xxxxxxxxxxxxx> > > Add a description, required properties, appropriate compatibles and > missing properties like clocks and clock-names which are not defined in > the text binding for all the SoCs that are supported by microchip. > > Signed-off-by: Durai Manickam KR <durai.manickamkr@xxxxxxxxxxxxx> > Signed-off-by: Charan Pedumuru <charan.pedumuru@xxxxxxxxxxxxx> > --- > Changes in v2: > - Renamed the yaml file to a compatible. > - Removed `|` and description for common properties. > - Modified the commit message. > - Dropped the label for the node in examples. > - Link to v1: https://lore.kernel.org/all/20240215-dmac-v1-1-8f1c6f031c98@xxxxxxxxxxxxx > --- > .../bindings/dma/atmel,at91sam9g45-dma.yaml | 67 ++++++++++++++++++++++ > .../devicetree/bindings/dma/atmel-dma.txt | 42 -------------- > 2 files changed, 67 insertions(+), 42 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml b/Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml > new file mode 100644 > index 000000000000..8d0d68786cbc > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Atmel Direct Memory Access Controller (DMA) > + > +maintainers: > + - Ludovic Desroches <ludovic.desroches@xxxxxxxxxxxxx> > + - Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> > + > +description: > + The Atmel Direct Memory Access Controller (DMAC) transfers data from a source > + peripheral to a destination peripheral over one or more AMBA buses. One channel > + is required for each source/destination pair. In the most basic configuration, > + the DMAC has one master interface and one channel. The master interface reads > + the data from a source and writes it to a destination. Two AMBA transfers are > + required for each DMAC data transfer. This is also known as a dual-access transfer. > + The DMAC is programmed via the APB interface. > + > +properties: > + compatible: > + oneOf: > + - enum: compatible: enum: You only have one option in your oneOf list. > + - atmel,at91sam9g45-dma > + - atmel,at91sam9rl-dma Blank line here please. > + reg: > + maxItems: 1
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