Some RZ/V2H SoC variants feature a Mali-G31 (GPU) and/or a Mali-C55 (ISP)
IP(s). Detect and inform about their presence during SoC identification.
Also detect PLL frequency and warn in case of mismatch.
Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
---
Changes:
v4: No changes
v3: New patch
drivers/soc/renesas/r9a09g057-sys.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a09g057-sys.c
index dc7885b340c4..18a79e68bade 100644
--- a/drivers/soc/renesas/r9a09g057-sys.c
+++ b/drivers/soc/renesas/r9a09g057-sys.c
@@ -13,12 +13,41 @@
#include "rz-sysc.h"
#include "rzg3e-sys.h"
+/* RZ/V2H-specific feature bits */
+#define SYS_LSI_PRR_GPU_DIS BIT(0)
+#define SYS_LSI_PRR_ISP_DIS BIT(4)
+
+static void rzv2h_sys_print_id(struct device *dev,
+ void __iomem *sysc_base,
+ struct soc_device_attribute *soc_dev_attr)
+{
+ bool gpu_enabled, isp_enabled;
+ u32 prr_val, mode_val;
+
+ prr_val = readl(sysc_base + SYS_LSI_PRR);
+ mode_val = readl(sysc_base + SYS_LSI_MODE);
+
+ /* Check GPU and ISP configuration */
+ gpu_enabled = !(prr_val & SYS_LSI_PRR_GPU_DIS);
+ isp_enabled = !(prr_val & SYS_LSI_PRR_ISP_DIS);
+
+ dev_info(dev, "Detected Renesas %s %s Rev %s%s%s\n",
+ soc_dev_attr->family, soc_dev_attr->soc_id, soc_dev_attr->revision,
+ gpu_enabled ? " with GE3D (Mali-G31)" : "",
+ isp_enabled ? " with ISP (Mali-C55)" : "");
+
+ /* Check CA55 PLL configuration */
+ if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
+ dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
+}
+
static const struct rz_sysc_soc_id_init_data rzv2h_sys_soc_id_init_data __initconst = {
.family = "RZ/V2H",
.id = 0x847a447,
.offset = SYS_LSI_DEVID,
.revision_mask = SYS_LSI_DEVID_REV,
.specific_id_mask = SYS_LSI_DEVID_SPECIFIC,
+ .print_id = rzv2h_sys_print_id,
};
const struct rz_sysc_init_data rzv2h_sys_init_data = {
--
2.25.1
