The CM3.5 device used in EyeQ6H SoCs incorrectly reports the status
for Hardware Cache Initialization (HCI). This commit adds the
compatible string for the CM to acknowledge this issue, which enables
the use of the second CPU cluster.
Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
---
arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
index 4a1a43f351d39625b520a16d035cacd2e29d157c..dabd5ed778b739b62f5c6e7348f1837a207dbb6c 100644
--- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
@@ -32,6 +32,10 @@ cpu_intc: interrupt-controller {
#interrupt-cells = <1>;
};
+ coherency-manager {
+ compatible = "mobileye,eyeq6-cm";
+ };
+
xtal: clock-30000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
--
2.45.2
