Manivannan, [ . . . ] > > > + phys = <&pcie1_phy>; > > > + phy-names = "pciephy"; > > > + > > > + interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>, > > > + <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>; > > > + interconnect-names = "pcie-mem", "cpu-pcie"; > > > > Can you check if the controller supports cache coherency? If so, you need to add > > 'dma-coherent'. > > Ok. Confirmed with h/w person. The controller doesn't support cache coherance. Thanks Varada
