On Mon, Jan 20, 2025 at 04:13:04AM +0530, Thippeswamy Havalige wrote: > Add AMD Versal2 MDB (Multimedia DMA Bridge) PCIe Root Port Bridge. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx> Couple of comments below. With those fixed, Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx> > --- > Changes in v2: > ------------- > - Modify patch subject. > - Add pcie host bridge reference. > - Modify filename as per compatible string. > - Remove standard PCI properties. > - Modify interrupt controller description. > - Indentation > > Changes in v3: > ------------- > - Modified SLCR to lower case. > - Add dwc schemas. > - Remove common properties. > - Move additionalProperties below properties. > - Remove ranges property from required properties. > - Drop blank line. > - Modify pci@ to pcie@ > > Changes in v4: > ------------- > - None. > > Changes in v5: > ------------- > - None. > Changes in v6: > -------------- > - Reduce dbi size to 4k. > - update register name to slcr. > --- > .../bindings/pci/amd,versal2-mdb-host.yaml | 121 ++++++++++++++++++ > 1 file changed, 121 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml > > diff --git a/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml > new file mode 100644 > index 000000000000..db751a51e63c > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/amd,versal2-mdb-host.yaml > @@ -0,0 +1,121 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller > + > +maintainers: > + - Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx> > + > +allOf: > + - $ref: /schemas/pci/pci-host-bridge.yaml# > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > + > +properties: > + compatible: > + const: amd,versal2-mdb-host > + > + reg: > + items: > + - description: MDB System Level Control and Status Register (SLCR) Base > + - description: configuration region > + - description: data bus interface > + - description: address translation unit register > + > + reg-names: > + items: > + - const: slcr > + - const: config > + - const: dbi > + - const: atu > + > + ranges: > + maxItems: 2 > + > + msi-map: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + interrupt-map-mask: > + items: > + - const: 0 > + - const: 0 > + - const: 0 > + - const: 7 > + > + interrupt-map: > + maxItems: 4 > + > + "#interrupt-cells": > + const: 1 > + > + interrupt-controller: > + description: identifies the node as an interrupt controller > + type: object > + additionalProperties: false > + properties: > + interrupt-controller: true > + > + "#address-cells": > + const: 0 > + > + "#interrupt-cells": > + const: 1 > + > + required: > + - interrupt-controller > + - "#address-cells" > + - "#interrupt-cells" > + > +required: > + - reg > + - reg-names > + - interrupts > + - interrupt-map > + - interrupt-map-mask > + - msi-map > + - "#interrupt-cells" > + - interrupt-controller > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + pcie@ed931000 { > + compatible = "amd,versal2-mdb-host"; > + reg = <0x0 0xed931000 0x0 0x2000>, > + <0x1000 0x100000 0x0 0xff00000>, > + <0x1000 0x0 0x0 0x1000>, > + <0x0 0xed860000 0x0 0x2000>; > + reg-names = "slcr", "config", "dbi", "atu"; > + ranges = <0x2000000 0x00 0xa8000000 0x00 0xa8000000 0x00 0x10000000>, I/O PCI address starts from 0. Also use 0x0 instead of 0x00 for consistency. - Mani -- மணிவண்ணன் சதாசிவம்
