From: Stefan Eichenberger <stefan.eichenberger@xxxxxxxxxxx> Currently, HDMI audio cannot play sound at a 44.1 kHz sample rate due to a clock frequency mismatch. This update resolves the issue by allowing the sai driver to change the clock parent to AUDIO_PLL_1 when the sample rate is 44.1 kHz. It also ensures that AUDIO_PLL_1 operates at the correct frequency for this configuration. Signed-off-by: Stefan Eichenberger <stefan.eichenberger@xxxxxxxxxxx> --- This patch is based on the following discussion: https://lore.kernel.org/all/20250113094654.12998-1-eichest@xxxxxxxxx/ We use the existing mechanisms and just add the missing clock configuration to our device tree. .../boot/dts/freescale/imx8-apalis-v1.1.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index a3fc945aea16..dbea1eefdeec 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -790,6 +790,22 @@ &sai1 { status = "okay"; }; +/* Apalis HDMI Audio */ +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>, <&aud_rec1_lpcg 0>; + assigned-clock-rates = <0>, <0>, <786432000>, <49152000>, <12288000>, + <722534400>, <45158400>, <11289600>, <49152000>; +}; + /* TODO: Apalis SATA1 */ /* Apalis SPDIF1 */ -- 2.45.2
