On 04/23/2015 01:41 AM, David Miller wrote:
Sigh... I'm seeing no way out of that then, only copying. :-(
What exactly is the device's restriction?
The frame data must be aligned on 32-bit boundary.
Any reasonable modern chip allows one of two things.
Either it allows arbitrary alignment of the start of the TX frame when DMA'ing.
_or_
It allows a variable number of pad bytes to be inserted by the driver before giving it to the card, which do not go onto the wire, in order to meet the device's DMA restrictions.
For example, if the packet is only 2 byte aligned, you set the "ignore offset" to 2 and push two zero bytes in front of the ethernet frame before giving it to the card.
I'm not seeing any padding logic on the TX path, only on the RX path (but it counts in 4-byte words, so seems quite useless).
If a chip made in this day and era cannot do one of those two things, this is beyond disappointing and is a massive engineering failure. Whoever designed this chip made no investigation into how their hardware is going to be actually used.
Too nad the Renesas SoC designers are not reading that. :-) WBR, Sergei -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
