The CM3.5 device used in EyeQ6H SoCs incorrectly reports the status
for Hardware Cache Initialization (HCI). This commit adds the
compatible string for the CM to acknowledge this issue, which enables
the use of the second CPU cluster.
Signed-off-by: Gregory CLEMENT <gregory.clement@xxxxxxxxxxx>
---
arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
index 1db3c3cda2e395025075387bcb66ea0737fd37f6..c6087bd8ca1d47855b8d93aa7e75e1fed219587b 100644
--- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
@@ -32,6 +32,10 @@ cpu_intc: interrupt-controller {
#interrupt-cells = <1>;
};
+ coherency-manager {
+ compatible = "mti,eyeq6-cm";
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
--
2.45.2
