Configure PBus base address and address mask in order to allow the hw
detecting if a given address is on PCIE0, PCIE1 or PCIE2.
Introduce binding for PBUS_CSR node available on EN7581 SoC.
---
Lorenzo Bianconi (2):
dt-bindings: arm: airoha: Add the pbus-csr node for EN7581 SoC
PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC
.../bindings/arm/airoha,en7581-pbus-csr.yaml | 41 ++++++++++++++++++++++
drivers/pci/controller/pcie-mediatek-gen3.c | 29 ++++++++++++++-
2 files changed, 69 insertions(+), 1 deletion(-)
---
base-commit: d02e16e4e05d5d2530a4836ca92318c6a6b21b01
change-id: 20250115-en7581-pcie-pbus-csr-994ab50984d7
Best regards,
--
Lorenzo Bianconi <lorenzo@xxxxxxxxxx>
