Current RT2880 device tree file is out of date and must be merged with real
device tree file used in openWRT project [0]. As a first iteration for this
changes, align the current file with the needed changes for system controller
from '6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")'.
[0]: https://github.com/openwrt/openwrt/blob/main/target/linux/ramips/dts/rt2880.dtsi
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
---
arch/mips/boot/dts/ralink/rt2880.dtsi | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi
index 8fc1987d9063..1f2ea3434324 100644
--- a/arch/mips/boot/dts/ralink/rt2880.dtsi
+++ b/arch/mips/boot/dts/ralink/rt2880.dtsi
@@ -1,4 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/mediatek,mtmips-sysc.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -25,9 +27,11 @@ palmbus@300000 {
#address-cells = <1>;
#size-cells = <1>;
- sysc@0 {
- compatible = "ralink,rt2880-sysc";
+ sysc: syscon@0 {
+ compatible = "ralink,rt2880-sysc", "syscon";
reg = <0x0 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
intc: intc@200 {
@@ -50,6 +54,8 @@ uartlite@c00 {
compatible = "ralink,rt2880-uart", "ns16550a";
reg = <0xc00 0x100>;
+ clocks = <&sysc RT2880_CLK_UARTLITE>;
+
interrupt-parent = <&intc>;
interrupts = <8>;
--
2.25.1
