On Wed, Jan 08, 2025 at 12:32:35PM -0600, Bjorn Helgaas wrote:
> On Thu, Jan 02, 2025 at 05:00:18PM +0530, Varadarajan Narayanan wrote:
> > From: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx>
> >
> > Add phy and controller nodes for pcie0_x1 and pcie1_x2.
>
> > + pcie1: pcie@18000000 {
> > + compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
> > + reg = <0x00088000 0x3000>,
> > + <0x18000000 0xf1d>,
> > + <0x18000f20 0xa8>,
> > + <0x18001000 0x1000>,
> > + <0x18100000 0x1000>,
> > + <0x0008b000 0x1000>;
> > + reg-names = "parf",
> > + "dbi",
> > + "elbi",
> > + "atu",
> > + "config",
> > + "mhi";
> > + device_type = "pci";
> > + linux,pci-domain = <1>;
> > + bus-range = <0x00 0xff>;
>
> This bus-range isn't needed, is it? pci_parse_request_of_pci_ranges()
> should default to 0x00-0xff if no bus-range property is present.
Ok.
>
> > + num-lanes = <2>;
> > + phys = <&pcie1_phy>;
> > + phy-names = "pciephy";
>
> I think num-lanes and PHY info are per-Root Port properties, not a
> host controller properties, aren't they? Some of the clock and reset
> properties might also be per-Root Port.
>
> Ideally, I think per-Root Port properties should be in a child device
> as they are here:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/mvebu-pci.txt?id=v6.12#n137
> but it looks like the num-lanes parsing is done in
> dw_pcie_get_resources(), which can only handle a single num-lanes per
> DWC controller, so maybe it's impractical to add a child device here.
>
> But I wonder if it would be useful to at least group the per-Root Port
> things together in the binding to help us start thinking about the
> difference between the controller and the Root Port(s).
This looks like a big change and might impact the existing
SoCs/platforms. To minimize the impact, should we continue
supporting the legacy method in addition to the new per-Root port
approach. Should we take this up separately? Kindly advice.
Thanks
Varada
