From: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
Add pinctrl device to support Amlogic A4 and add uart pinconf.
Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
---
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 133 ++++++++++++++++++++++++++++
1 file changed, 133 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index de10e7aebf21..8eb95580d64a 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -5,6 +5,7 @@
#include "amlogic-a4-common.dtsi"
#include <dt-bindings/power/amlogic,a4-pwrc.h>
+#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
/ {
cpus {
#address-cells = <2>;
@@ -48,3 +49,135 @@ pwrc: power-controller {
};
};
};
+
+&apb {
+ periphs_pinctrl: pinctrl {
+ compatible = "amlogic,pinctrl-a4";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpiox: gpio@4100 {
+ reg = <0 0x4100 0 0x40>,
+ <0 0x400c 0 0xc>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ bank-number = <AMLOGIC_GPIO_X>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 18>;
+ };
+
+ gpiot: gpio@4140 {
+ reg = <0 0x4140 0 0x40>,
+ <0 0x402c 0 0xc>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ bank-number = <AMLOGIC_GPIO_T>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_T<<8) 23>;
+ };
+
+ gpiod: gpio@4180 {
+ reg = <0 0x4180 0 0x40>,
+ <0 0x4040 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ bank-number = <AMLOGIC_GPIO_D>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 16>;
+ };
+
+ gpioe: gpio@41c0 {
+ reg = <0 0x41c0 0 0x40>,
+ <0 0x4048 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ bank-number = <AMLOGIC_GPIO_E>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
+ };
+
+ gpiob: gpio@4240 {
+ reg = <0 0x4240 0 0x40>,
+ <0 0x4000 0 0x8>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ bank-number = <AMLOGIC_GPIO_B>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
+ };
+
+ gpioao: gpio@8e704 {
+ reg = <0 0x8e704 0 0x16>,
+ <0 0x8e700 0 0x4>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ bank-number = <AMLOGIC_GPIO_AO>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_AO<<8) 7>;
+ };
+
+ test_n: gpio@8e744 {
+ reg = <0 0x8e744 0 0x20>;
+ reg-names = "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ bank-number = <AMLOGIC_GPIO_TEST_N>;
+ gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
+ };
+
+ func-uart-a {
+ uart_a_default: group-uart-a-pins1 {
+ pinmux= <AML_PINMUX(AMLOGIC_GPIO_X, 11, 1)>,
+ <AML_PINMUX(AMLOGIC_GPIO_X, 12, 1)>,
+ <AML_PINMUX(AMLOGIC_GPIO_X, 13, 1)>,
+ <AML_PINMUX(AMLOGIC_GPIO_X, 14, 1)>;
+ };
+
+ group-uart-a-pins2 {
+ pinmux= <AML_PINMUX(AMLOGIC_GPIO_D, 2, 3)>,
+ <AML_PINMUX(AMLOGIC_GPIO_D, 3, 3)>;
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ func-uart-b {
+ uart_b_default: group-uart-b-pins {
+ pinmux= <AML_PINMUX(AMLOGIC_GPIO_E, 0, 3)>,
+ <AML_PINMUX(AMLOGIC_GPIO_E, 1, 3)>;
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ func-uart-d {
+ uart_d_default: group-uart-d-pins1 {
+ pinmux= <AML_PINMUX(AMLOGIC_GPIO_T, 18, 4)>,
+ <AML_PINMUX(AMLOGIC_GPIO_T, 19, 4)>;
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+
+ group-uart-d-pins2 {
+ pinmux= <AML_PINMUX(AMLOGIC_GPIO_T, 7, 2)>,
+ <AML_PINMUX(AMLOGIC_GPIO_T, 8, 2)>,
+ <AML_PINMUX(AMLOGIC_GPIO_T, 9, 2)>,
+ <AML_PINMUX(AMLOGIC_GPIO_T, 10, 2)>;
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ func-uart-e {
+ uart_e_default: group-uart-e-pins {
+ pinmux= <AML_PINMUX(AMLOGIC_GPIO_T, 14, 3)>,
+ <AML_PINMUX(AMLOGIC_GPIO_T, 15, 3)>,
+ <AML_PINMUX(AMLOGIC_GPIO_T, 16, 3)>,
+ <AML_PINMUX(AMLOGIC_GPIO_T, 17, 3)>;
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+ };
+ };
+};
--
2.37.1
