On Mon, Jan 13, 2025 at 01:52:13PM -0800, Melody Olvera wrote:
> From: Wesley Cheng <quic_wcheng@xxxxxxxxxxx>
>
> Enable USB support on SM8750 MTP and QRD variants. SM8750 has a QMP combo
> PHY for the SSUSB path, and a M31 eUSB2 PHY for the HSUSB path.
>
> Signed-off-by: Wesley Cheng <quic_wcheng@xxxxxxxxxxx>
> Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 24 ++++++
> arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 24 ++++++
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 134 ++++++++++++++++++++++++++++++++
Separate SoC and board patches.
> 3 files changed, 182 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> index 9e3aacad7bdab6848e86f8e45e04907e1c752a07..059eccbbc3fb05fc8806e36d35dc469d44443a26 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> @@ -792,3 +792,27 @@ &tlmm {
> &uart7 {
> status = "okay";
> };
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "peripheral";
> +};
> +
> +&usb_1_hsphy {
> + vdd-supply = <&vreg_l2d_0p88>;
> + vdda12-supply = <&vreg_l3g_1p2>;
> +
> + phys = <&pmih0108_eusb2_repeater>;
> +
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy {
> + vdda-phy-supply = <&vreg_l3g_1p2>;
> + vdda-pll-supply = <&vreg_l2d_0p88>;
> +
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
> index f77efab0aef9bab751a947173bcdcc27df7295a8..01c0af643626917614fbd68cf8962ef947ca6548 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
> @@ -790,3 +790,27 @@ &tlmm {
> &uart7 {
> status = "okay";
> };
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "peripheral";
> +};
> +
> +&usb_1_hsphy {
> + vdd-supply = <&vreg_l2d_0p88>;
> + vdda12-supply = <&vreg_l3g_1p2>;
> +
> + phys = <&pmih0108_eusb2_repeater>;
> +
> + status = "okay";
> +};
> +
> +&usb_dp_qmpphy {
> + vdda-phy-supply = <&vreg_l3g_1p2>;
> + vdda-pll-supply = <&vreg_l2d_0p88>;
> +
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..54522fd3d0e11c3cff02beaf1d249fe654cacc0f 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> #include <dt-bindings/power/qcom,rpmhpd.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> @@ -1966,6 +1967,139 @@ lpass_lpicx_noc: interconnect@7420000 {
> #interconnect-cells = <2>;
> };
>
> + usb_1_hsphy: phy@88e3000 {
> + compatible = "qcom,sm8750-m31-eusb2-phy";
> + reg = <0x0 0x88e3000 0x0 0x29c>;
> +
> + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
> + clock-names = "ref";
> +
> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + usb_dp_qmpphy: phy@88e8000 {
> + compatible = "qcom,sm8750-qmp-usb3-dp-phy";
> + reg = <0x0 0x088e8000 0x0 0x3000>;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "usb3_pipe";
> +
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> + reset-names = "phy",
> + "common";
> +
> + power-domains = <&gcc GCC_USB3_PHY_GDSC>;
> +
> + #clock-cells = <1>;
> + #phy-cells = <1>;
Missing orientation-switch and ports{} description.
> +
> + status = "disabled";
> + };
> +
> + usb_1: usb@a6f8800 {
> + compatible = "qcom,sm8750-dwc3", "qcom,dwc3";
> + reg = <0x0 0x0a6f8800 0x0 0x400>;
> + status = "disabled";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&tcsrcc TCSR_USB3_CLKREF_EN>;
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "xo";
> +
> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pwr_event",
> + "hs_phy_irq",
> + "dp_hs_phy_irq",
> + "dm_hs_phy_irq",
> + "ss_phy_irq";
> +
> + power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
> + required-opps = <&rpmhpd_opp_nom>;
> +
> + resets = <&gcc GCC_USB30_PRIM_BCR>;
> +
> + interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
> + interconnect-names = "usb-ddr", "apps-usb";
> +
> + usb_1_dwc3: usb@a600000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x0a600000 0x0 0xe000>;
> +
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> +
> + iommus = <&apps_smmu 0x40 0x0>;
> +
> + phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
> + phy-names = "usb2-phy", "usb3-phy";
> +
> + snps,hird-threshold = /bits/ 8 <0x0>;
> + snps,usb2-gadget-lpm-disable;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + snps,dis-u1-entry-quirk;
> + snps,dis-u2-entry-quirk;
> + snps,is-utmi-l1-suspend;
> + snps,usb3_lpm_capable;
> + snps,usb2-lpm-disable;
> + snps,has-lpm-erratum;
> + tx-fifo-resize;
> +
> + dr_mode = "peripheral";
This goes to the board files.
> +
> + dma-coherent;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + usb_1_dwc3_hs: endpoint {
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + usb_1_dwc3_ss: endpoint {
QMP endpoint.
> + };
> + };
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm8750-pdc", "qcom,pdc";
> reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
>
> --
> 2.46.1
>
--
With best wishes
Dmitry
