On Thu, Jan 02, 2025 at 10:37:36AM -0800, E Shattow wrote:
> StarFive JH7110 contains a Cadence USB2.0+USB3.0 controller IP block that
> may exclusively use pciephy0 for USB3.0 connectivity. Add the register
> offsets for the driver to enable/disable USB3.0 on pciephy0.
>
> Signed-off-by: E Shattow <e@xxxxxxxxxxxx>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 0d8339357bad..75ff07303e8b 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -611,6 +611,8 @@ usbphy0: phy@10200000 {
> pciephy0: phy@10210000 {
> compatible = "starfive,jh7110-pcie-phy";
> reg = <0x0 0x10210000 0x0 0x10000>;
> + starfive,sys-syscon = <&sys_syscon 0x18>;
> + starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
Why weren't these added in the first place? Minda, do you know?
> #phy-cells = <0>;
> };
>
> --
> 2.45.2
>
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