On Thu, Jan 09, 2025 at 01:38:13PM +0200, Vladimir Kondratiev wrote: > Document optional property "riscv,hart-indexes" > > Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@xxxxxxxxxxxx> > Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx> > --- > .../bindings/interrupt-controller/riscv,aplic.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > index 190a6499c932..bef00521d5da 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml > @@ -91,6 +91,14 @@ properties: > Firmware must configure interrupt delegation registers based on > interrupt delegation list. > > + riscv,hart-indexes: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 16384 > + description: > + A list of hart indexes that APLIC should use to address each hart > + that is mentioned in the "interrupts-extended" Wouldn't using the 'cpus' property linking to each cpu/hart node work? Rob
