Hello Andrew, All,
Le 09/01/2025 à 16:58, Andrew Davis a écrit :
> On 1/9/25 4:26 AM, Romain Naour wrote:
>> From: Romain Naour <romain.naour@xxxxxxx>
>>
>> Unlike the SK-TDA4VM (k3-j721e-sk) board, there is no clock generator
>> (CDCI6214RGET) on the BeagleBone AI-64 (k3-j721e-beagleboneai64) to
>> provide PCIe refclk signal to PCIe Endponts. So the ACSPCIE module must
>> provide refclk through PCIe_REFCLK pins.
>>
>> Use the new "ti,syscon-acspcie-proxy-ctrl" property to enable ACSPCIE
>> module's PAD IO Buffers.
>>
>> Cc: Siddharth Vadapalli <s-vadapalli@xxxxxx>
>> Signed-off-by: Romain Naour <romain.naour@xxxxxxx>
>> ---
[...]
>> ---
>> arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 5 +++++
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 10 ++++++++--
>> 2 files changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/
>> boot/dts/ti/k3-j721e-beagleboneai64.dts
>> index fb899c99753e..741ad2ba6fdb 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
>> @@ -859,6 +859,11 @@ &pcie1_rc {
>> num-lanes = <2>;
>> max-link-speed = <3>;
>> reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
>> + /*
>> + * There is no on-board or external reference clock generators,
>> + * use refclk from the ACSPCIE module's PAD IO Buffers.
>> + */
>> + ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>;
>> };
>> &ufs_wrapper {
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/
>> ti/k3-j721e-main.dtsi
>> index af3d730154ac..32a232a90100 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -5,6 +5,7 @@
>> * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
>> */
>> #include <dt-bindings/phy/phy.h>
>> +#include <dt-bindings/phy/phy-cadence.h>
>> #include <dt-bindings/phy/phy-ti.h>
>> #include <dt-bindings/mux/mux.h>
>> @@ -82,6 +83,11 @@ ehrpwm_tbclk: clock-controller@4140 {
>> reg = <0x4140 0x18>;
>> #clock-cells = <1>;
>> };
>> +
>> + acspcie0_proxy_ctrl: syscon@18090 {
>> + compatible = "ti,j721e-acspcie-proxy-ctrl", "syscon";
>> + reg = <0x18090 0x4>;
>> + };
>
> You'll still need to add to the J721e system controller binding or this
> will throw a DT check warning, something like this:
>
> diff --git a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-
> controller.yaml b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-
> controller.yaml
> index 378e9cc5fac2a..3323f3bc976e0 100644
> --- a/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/ti/ti,j721e-system-controller.yaml
> @@ -68,6 +68,12 @@ patternProperties:
> description:
> The node corresponding to SoC chip identification.
>
> + "^acspcie-ctrl@[0-9a-f]+$":
> + type: object
> + $ref: /schemas/mfd/syscon.yaml#
> + description:
> + This is the ASPCIe control region.
> +
> required:
> - compatible
> - reg
Thanks!
To fix the warning I had to use "^syscon@[0-9a-f]+$" instead.
During the review, "syscon@" was recommended instead of "acspcie-ctrl@" [1]
acspcie0_proxy_ctrl: syscon@18090 {
[1]
https://lore.kernel.org/linux-devicetree/5e2d2174-44a7-4143-8562-4dcdb5ad6c94@xxxxxxxxxx/
Best regards,
Romain
>
>> };
>> main_ehrpwm0: pwm@3000000 {
>> @@ -979,8 +985,8 @@ pcie1_rc: pcie@2910000 {
>> max-link-speed = <3>;
>> num-lanes = <2>;
>> power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>> - clocks = <&k3_clks 240 1>;
>> - clock-names = "fck";
>> + clocks = <&k3_clks 240 1>, <&serdes1 CDNS_SIERRA_DERIVED_REFCLK>;
>> + clock-names = "fck", "pcie_refclk";
>> #address-cells = <3>;
>> #size-cells = <2>;
>> bus-range = <0x0 0xff>;
