On Tue, Apr 21, 2015 at 10:27:13AM +0800, Koro Chen wrote: > The SRAM size to be used is defined by params_buffer_bytes(params), not > fixed (of course limited by the actual available SRAM size on HW), so > the latency should be the same compared to a DRAM having the same size. Right, some systems have the SRAM as essentially a big FIFO but this doesn't have that problem. > The SRAM can be used by any memif, and that's why the plan was let DT > make the decision. OK, if it's for any interface rather than just DL1 like Sascha said then it does need to be selectable, but DT doesn't seem the platce to do it.
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