On 2024/12/30 21:27, Konrad Dybcio wrote:
On 26.12.2024 8:03 AM, Yongxing Mou wrote:
On 2024/12/6 5:36, Konrad Dybcio wrote:
On 27.11.2024 11:45 AM, Yongxing Mou wrote:
Add device tree nodes for the DPTX0 controller with their
corresponding PHYs found on Qualcomm QCS8300 SoC.
Signed-off-by: Yongxing Mou <quic_yongmou@xxxxxxxxxxx>
---
[...]
+ mdss_dp0_phy: phy@aec2a00 {
+ compatible = "qcom,qcs8300-edp-phy";
+
+ reg = <0x0 0x0aec2a00 0x0 0x200>,
0x19c
got it.thanks.
+ <0x0 0x0aec2200 0x0 0xd0>,
0xec
got it.thanks.
+ <0x0 0x0aec2600 0x0 0xd0>,
0xec
For lengths
got it.thanks.
+ <0x0 0x0aec2000 0x0 0x1c8>;
This one's correct
+
+ clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
power-domains = <&rpmhpd RPMHPD_MX>;
emm,we use RPMHPD_MMCX in qcs8300 mdss and dpu..
(or maybe even MXC?)
Please verify what backs the PHY and update accordingly
Konrad
Thank you for the reminder. it should use RPMHPD_MX.My previous
understanding that using MMCX was incorrect.
