This patch set adds PCIe Root Port support for the Agilex family of FPGA chips. Version 3 of this patch set removes patches that have been accepted. Patch 1: Add new compatible strings for the three variants of the Agilex PCIe controller IP. Patch 2: Add a label to the soc@0 device tree node to be used by patch 5. Patch 3: Add base dtsi for PCIe Root Port support of the Agilex family of chips. Patch 4: Add dts enabling PCIe Root Port support on an Agilex F-series Development Kit. Patch 5: Update Altera PCIe controller driver to support the Agilex family of chips. D M, Sharath Kumar (1): PCI: altera: Add Agilex support Matthew Gerlach (4): dt-bindings: PCI: altera: Add binding for Agilex arm64: dts: agilex: add soc0 label arm64: dts: agilex: add dtsi for PCIe Root Port arm64: dts: agilex: add dts enabling PCIe Root Port .../bindings/pci/altr,pcie-root-port.yaml | 9 + arch/arm64/boot/dts/intel/Makefile | 1 + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- .../socfpga_agilex7f_socdk_pcie_root_port.dts | 16 ++ .../intel/socfpga_agilex_pcie_root_port.dtsi | 55 ++++ drivers/pci/controller/pcie-altera.c | 246 +++++++++++++++++- 6 files changed, 319 insertions(+), 10 deletions(-) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi -- 2.34.1
