Adreno X1-85 has an additional bit which is at a non-contiguous
location in qfprom. Add support for this new "hi" bit along with
the speedbin mappings.
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = {
.gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_256G,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 263, 1 },
+ { 315, 0 },
+ ),
.preempt_record_size = 4192 * SZ_1K,
}, {
.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
int adreno_read_speedbin(struct device *dev, u32 *speedbin)
{
- return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
+ u32 hi_bits = 0;
+ int ret;
+
+ ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
+ if (ret)
+ return ret;
+
+ /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */
+ ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits);
+ if (ret != -ENOENT)
+ return ret;
+
+ *speedbin |= (hi_bits << 8);
+ return 0;
}
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
--
2.45.2
