On Fri, Nov 22, 2024 at 01:19:22PM +0530, Qingqing Zhou wrote:
> Add the Adreno GPU SMMU node for QCS615 platform.
>
Please resubmit this in a series together with gpucc, gmu and gpu nodes.
Regards,
Bjorn
> Signed-off-by: Qingqing Zhou <quic_qqzhou@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 56af38d4f75f..4e0f26563db9 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -528,6 +528,33 @@
> #power-domain-cells = <1>;
> };
>
> + adreno_smmu: iommu@50a0000 {
> + compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu",
> + "qcom,smmu-500", "arm,mmu-500";
> + reg = <0x0 0x50a0000 0x0 0x10000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> + dma-coherent;
> +
> + power-domains = <&gpucc CX_GDSC>;
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
> + clock-names = "mem",
> + "hlos",
> + "iface";
> +
> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> dc_noc: interconnect@9160000 {
> reg = <0x0 0x09160000 0x0 0x3200>;
> compatible = "qcom,qcs615-dc-noc";
> --
> 2.17.1
>
