On Sat, 21 Dec 2024 20:47:58 +0530, Jagan Teki wrote:
> The Edgeble 6TOPS modules has configured the PCIe3.0 with
> - 2 lanes on Port1 of pcie3x2 controller for M.2 M-Key
> - 2 lanes on Port0 of pcie3x4 controller for B and E-Key
>
> The, current DT uses opposite controller nodes that indeed uses
> incorrect reset, regulator nodes.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: Fix PCIe3 handling for Edgeble-6TOPS Modules
commit: e2ee8a440869281620fbcacdca6e13cbeebcc1be
Best regards,
--
Heiko Stuebner <heiko@xxxxxxxxx>
